This invention is in the field of digital systems, and is more specifically directed to the communication of digital data streams among integrated circuits in such systems.
In many digital systems, digital data must be communicated among various integrated circuits. While data communication may be asynchronous, synchronous communication is preferred for high data rates. A common approach to synchronous data communication involves the use of a clock signal, generated either by the data source or the data destination, that the data stream is synchronized with. The source and destination integrated circuits synchronize their output and input operations with the communicated clock signal, ensuring high reliability communication.
FIG. 1a illustrates a conventional instance of data communication between a data source and a data destination (or data “sink”). In this example, the source is video decoder 2, which forwards an eight-bit data stream, in this example, over bus D to video encoder 4 (e.g., an MPEG encoder). In this example, video decoder 2 generates clock signal CLK1 synchronously with the data stream on bus D. In some applications, the data destination generates the clock signal; a well-known example of this approach is conventional memory access, in which the data destination applies clock signals to the memory to effect the read and write operations. Referring back to FIG. 1a, video encoder 4 receives both the eight-bit data stream on bus D and clock signal CLK1, and synchronizes its buffering and latching of the data values in the data stream with edges of clock signal CLK1.
FIG. 1b illustrates the relative tiling of data on bus D with clock signal CLK1 in this example. As shown in FIG. 1b, data bus D presents sequential data words DATAk et seq. Clock signal CLK1 is synchronized with this stream of data words, in this example with a rising edge of clock signal CLK1 occurring when a valid data word DATAk is present on data bus D. In the example shown in FIG. 1b, video decoder 2 presents valid data on data bus D at a setup time tSU prior to the rising edge of clock signal CLK1, and maintains valid data on data bus D for a hold time tH after the rising edge of clock signal CLK1; these setup and hold times tSU and tH, respectively, must exceed the input data setup and data hold time specifications for video encoder 4 in order for reliable communication to occur.
As fundamental in the art, system performance is determined in large part by the rate at which data can be input to, output from, and communicated within, the system. Maximization of this performance is, in general, achieved by increasing the data communication rate to match the full processing capacity of the various components in the system.
By way of further background, so-called “dual-data-rate” (“DDR”) memories are known in the art. DDR memories, such as DDR synchronous dynamic random access memories (SDRAMS), respond to both the rising and falling edges of the clock signal, such that the data stream is at twice the frequency of the clock signal. FIG. 1c illustrates such a DDR data stream, in which data words DATAk et seq. are provided from the data source in a synchronous manner with both edges of clock signal CLK1. This dual data rate approach doubles the data rate of the communicated data stream without increasing the number of bus lines or integrated circuit input and output terminals, as compared to the conventional components of FIG. 1a. However, both the source and destination of the data stream must operate according to the dual data rate approach in order for valid communications to occur. In addition, the constraints on the data input and output circuitry (i.e., the setup and hold times achievable at the data source, and acceptable at the data destination) tighten in this DDR mode, relative to the single edge clocking of FIG. 1b. Skew in the timing of the various output bit drivers relative to one another must also be tightly controlled in this DDR operation.
By way of further background, the communication of multiple data streams from a single source component is known, particularly in the field of video decoding. Multiple data streams are especially useful in applications such as video surveillance for security purposes. As is well known in this field, it is useful for a human security officer to simultaneously view images from multiple surveillance cameras, typically by way of a single video display that shows several camera views in a “split-screen” manner. The simultaneous display of four to sixteen video camera images is well known. This split-screen display need not be of maximum resolution, and as such the images are typically “scaled” to a smaller image area (in terms of pixels) for split-screen display. However, modern video security systems also record the images from all of the cameras, preferably in full resolution to permit investigative use of recorded images. Accordingly, modern video security systems utilize both scaled image data (lower resolution) and unscaled image data (full resolution).
In one conventional approach, unscaled video data is provided by a video decoder to a digital signal processor (DSP). The DSP then processes this unscaled video data to generate an unscaled output for recording, and also scaled video signals for split-screen display. But the computational capacity of conventional DSP devices may not be sufficient to perform this processing for real-time display and recording, especially if multiple video cameras and inputs are to be recorded and displayed. It is therefore preferable for the video decoder to produce multiple video data streams, at multiple scalings, to a downstream component such as an encoder.
According to one conventional approach, two data streams may be separately output from the source, each with its own clock signal, for separate receipt and processing at the destination. This approach is illustrated in FIG. 1d, in which video decoder 2′ drives one data stream over bus D1, in combination with clock signal CLK1, and a second data stream over bus D2 in combination with clock signal CLK2. video encoder 4′ receives both data streams over buses D1, D2, and both clock signals CLK1, CLK2, and includes multiple encoding circuitry for processing each data stream.
However, this conventional approach requires each of video decoder 2′ and video encoder 4′ to include additional input and output terminals, or “pins”, to accommodate the additional data bus D2 and the additional clock signal CLK2. Considering that many modern integrated circuits already have hundreds of pins, the adding of still additional pins is discouraged. Not only must additional pins be provided in this conventional approach, but the circuit board onto which the source and destination components are implemented must also provide additional conductors (and the required spacing between conductors), which undesirably increases the circuit board area and the effects of parasitic inductance and capacitance.
According to another conventional approach, as described in a preliminary data sheet for the TW2802/4 Multiple Video Decoder, published by Techwell, Inc., two data streams (e.g., a video data stream that is communicated in two different video scalings) are interleaved into a double data rate stream. FIG. 1e illustrates this conventional approach. As shown in FIG. 1e, double data rate clock signal CLK2X is provided, in this case by video decoder 2 of FIG. 1a, in combination with interleaved data streams DS1, DS2. Double data rate clock signal CLK2X may be generated by doubling the frequency of a conventional video clock signal (e.g., CLK1 of FIGS. 1b and 1c), or otherwise. Data stream DS1 is presented in alternate cycles of double data rate clock signal CLK2X, with data stream DS2. In this example, the rising edge of double data rate clock signal CLK2X permits destination video encoder 4 to clock in a valid data state then present on data bus D.
The conventional approach illustrated in FIG. 1e results in the communication of two data streams, each at the same effective video rate as in the conventional arrangement of FIG. 1b. For example, the video communication format according to the well-known industry standard ITU-R BT.656 communicates video data at 27 MHz. The interleaved approach of FIG. 1e communicates the two data streams DS1, DS2, each at 27 MHz, by generating the double data rate (54 MHz) interleaved data stream on bus D, in combination with double data rate clock signal CLK2X (also at 54MHz). The destination (e.g., video encoder 4 of FIG. 1a) can then separate the two data streams from one another. As mentioned above, this approach is known to be beneficial for communicating video signals corresponding to two different image scalings, as is useful in security video applications in which a video sequence is communicated at full resolution for recording, and is also communicated at a reduced resolution version for display. This communication of two data streams is accomplished without requiring the additional pins and circuit board conductors that are necessary in the conventional approach of FIG. 1d. 
However, this approach of FIG. 1e requires not only the source (e.g., video decoder 2 of FIG. 1a) to be capable of transmitting the interleaved data streams at 54 MHz and the double data rate clock signal CLK2X, but also requires the destination (e.g., video encoder 4 of FIG. 1a) to receive and separate the two interleaved data streams from one another at the higher data rate, synchronously with double data rate clock signal CLK2X. The interleaved approach of FIG. 1e is therefore not compatible with “legacy” video components, such as those MPEG encoders and other integrated circuits that operate according to the ITU-R BT.656 standard. The widespread applicability of this approach is therefore quite limited.